1. Field of the Invention
An integrated circuit includes a voltage-tolerant output buffer.
2. Description of Prior Art
In the operation of integrated circuits, and integrated circuit (IC) that is fabricated for use with a given power supply voltage must often interface with other ICs that operate at a higher voltage. For example, an IC fabricated in a 3.3 technology must often operate with 5 volt signals supplied to its input/output bondpads from other devices. This may create reliability problems, since the maximum source-to-drain voltage, and gate oxide voltage for MOS transistors formed on the IC are typically not intended to withstand the higher voltage levels. A well-known prior-art circuit that allows an output buffer made in a 3.3 volt technology to tolerate a 5 volt signal on its output bondpad is shown in FIG. 1. A digital data signal "A" from circuitry on the IC is applied to the buffer input node 118. The buffer is placed in either the "tri-state" (i.e., high output impedance) or the normal mode of operation by an enable signal "EN" on node 117. When EN is low, the inverter 115 and NOR gate 116 place a low voltage on the gate of n-channel transistor 112, turning it off. Similarly, the NAND gate 102 places a high voltage on the gate of the p-channel transistor 103, turning it off. This allows the bondpad 101 to function as an input bondpad for input circuitry (not shown) on the same IC as the output buffer. When EN is high, the gates 102 and 116 are allowed to transmit data signals from node 118 to the transistors 103 and 112 to provide for the "normal" mode of operation.
In the normal mode of operation, with no external voltage applied to the bondpad 101, the circuit 100 operates as follows: The output of the NAND gate 102 is applied to the gate of transistor 103 through a transmission-gate made of transistors 104 and 105. Transistor 104 has its gate connected to V.sub.DD ; thus transistor 104 is always on. However, it cannot transmit a voltage higher than V.sub.DD -V.sub.tn from node 106 to node 107. Therefore a p-channel transistor 105 is added in parallel to ensure that node 107 can pull all the way up to V.sub.DD, and thus turn the buffer pull-up transistor 103 off. In normal operation, the gate of 105 is held at ground, turning it on. The device 108 shown in FIG. 1 is a resistor; however a transistor or group of transistors might be used in its place. For example, the use of one or more serially-connected n-channel transistors having their gates connected to V.sub.DD may be used as the resistor 108. Transistors 109 and 110 have their gates connected to V.sub.DD, and so are usually off in operation, except as discussed below. The protective transistor 111 also has its gate connected to V.sub.DD. The purpose of this device is to protect the buffer pull-down transistor 112 against a high voltage on the bondpad 101, since protective transistor 111 prevents node 113 from ever rising above V.sub.DD -V.sub.tn, where V.sub.tn is the threshold voltage of n-channel MOS transistors on the IC.
When a high voltage is applied to the bondpad 101 of the tri-stated buffer, transistors 109 and 110 will turn on at a voltage equal to V.sub.DD +V.sub.tp, where V.sub.tp is the threshold voltage of p-channel MOS transistors on the IC. When this occurs, the bondpad voltage will be applied to node 107 through transistor 109, and to node 114 through transistor 110. If the on resistance of transistor 110 is much less that that of resistor 108, the voltage on the gate of transistor 105 will turn that transistor off. This is desirable to ensure that the bondpad voltage which is applied to node 107 does not "shoot-through" transistor 105 and be applied to the NAND gate 102, which could damage it.